After semiconductor integrated circuit technology enters into technical node of 90 nm feature size, maintaining or improving transistor performance is becoming more and more challenging. In the current mainstream technology, the performance of PMOS is improved by epitaxially growing germanium-silicon in trenches of source/drain regions to provide a compressive stress to press the channel region of the transistor. Silicon-carbon is epitaxially grown in source/drain regions in order to improve the performance of NPMOS. Referring to FIG. 1, which shows a schematic drawing of a prior art transistor structure having epitaxial source/drain regions, trenches of the source/drain regions are formed by etching a substrate 1, and germanium-silicon or silicon-carbon is epitaxially grown to form epitaxial source/drain regions 2, thereby providing a stress to the channel region.
In devices with small size, boron (B) in source/drain regions of PMOS will easily diffuse from the source/drain regions into the substrate and channel region, causing SCE (Short Channel Effect) and DIBL (Drain Induction Barrier Lower) effects to increase the resistance of the source/drain regions and reducing the breakdown voltage between source and drain. In addition, if boron diffuses from source/drain extension regions into a gate insulating layer, the electrical properties of the gate insulating layer will become unstable. Meanwhile, the diffusion of boron from the source/drain regions will result in an increase of the electrons of the source/drain regions. All the above three aspects will degrade the electrical performance of the devices. The epitaxial germanium-silicon is doped with boron to reduce the serial resistance and the contact resistance, but boron with a high content in the epitaxial germanium-silicon might diffuse into the channel region. In PMOS, boron diffusing into the channel may result in a reduction of the threshold voltage in devices with small size.
In order to prevent diffusion of boron, the currently used method is HALO implantation. The implanted particles may be phosphor or arsenic, and the dosage is generally greater than 3e13cm−3. If the HALO implantation is performed before the epitaxial growth, the high dosage implantation may destroy the crystal structure at the surfaces of the source/drain trenches, thus influencing the subsequent epitaxial growth of germanium-silicon in the source/drain regions; if the implantation is performed after the epitaxial growth, the high dosage implantation will cause a release of the stress of the epitaxial layer, thus reducing the source/drain stress and weakening the effects of the source/drain stress suppressing SCE and DIBL. Meanwhile, a more profound influence is that even the HALO implantation cannot completely control the boron diffusion, and a short channel effect will occur. In addition, there is also a method at present, including implanting carbon ion into the source/drain silicon trenches as a barrier layer for preventing the boron diffusion, then performing a HALO implantation of a small dosage as a supplement for preventing the boron diffusion. This method can alleviate the damage to the surfaces of the source/drain silicon trenches caused by HALO, but it causes a new problem of damage to the source/drain silicon trenches by carbon implantation, meanwhile, in order to repair the damage to the surfaces of the source/drain trenches caused by the implantation, annealing is required in said process, which in turn results in a re-distribution of the doping element and makes the electrical properties of the device unstable. Therefore, there is a need for a new manufacturing method for a transistor having epitaxial source/drain regions to solve the above problems and to better ensure the good performance of the transistor.